ICM7170 Datasheet, PDF (10/14 Pages) Intersil Corporation – Microprocessor-Compatible, Real-Time Clock

IC_ICM_M77₁1₇7₀0
POSITIVE SUPPLY RAIL
(+5V)
V_DD
V_DD
BATTERY
PIN 23
R2
V_BACK
2K
PIN 14
V_SS
≅ V_TH 1.0V
V_DD
+ ^{CMOS COMPARATOR}
-
V_IG
I/O DISABLE
V_IG
INTERNAL GROUND
PIN 13
DIGITAL GROUND
FIGURE 6. SIMPLIFIED ICM7170 BATTERY BACKUP CIRCUIT
Time Synchronization
Time synchronization is achieved through bit D3 of the
Command Register, which is used to enable or disable the
100Hz clock from the counters. A logic “1” allows the counters
to function and a logic “0” disables the counters. To accurately
set the time, a logic “0” should be written into D3 and then the
desired times entered into the appropriate counters. The clock
is then started at the proper time by writing a logic “1” into D3 of
the Command Register.
Latched Data
To prevent ambiguity while the processor is gathering data from
the registers, the ICM7170 incorporates data latches and a
transparent transition delay circuit.
By accessing the 100ths of seconds counter an internal
store signal is generated and data from all the counters is
transferred into a 36-bit latch. A transition delay circuit will
delay a 100Hz transition during a READ cycle. The data
stored by the latches is then available for further processing
until the 100ths of seconds counter is read again. If a RD
signal is wider than 0.01s, 100Hz counts will be ignored.
Control Lines
The RD, WR, and CS signals are active low inputs. Data is
placed on the bus from counters or registers when RD is a
logic “0”. Data is transferred to counters or registers when
WR is a logic “0”. RD and WR must be accompanied by a
logical “0” CS as shown in Figures 2 and 3. The ICM7170
will also work satisfactorily with CS grounded. In this mode,
access to the ICM7170 is controlled by RD and WR only.
With the ALE (Address Latch Enable) input, the ICM7170
can be interfaced directly to microprocessors that use a
multiplexed address/data bus by connecting the address
lines A0 - A4 to the data lines D0 - D4. To address the chip,
the address is placed on the bus and ALE is strobed. On the
falling edge, the address and CS information is read into the
address latch and buffer. RD and WR are used in the same
way as on a non-multiplexed bus. If a non-multiplexed bus is
used, ALE should be connected to V_DD.
Test Mode
The test mode is entered by setting D5 of the Command
Register to a logic “1”. This connects the 100Hz counter
directly to the oscillator’s output.
Oscillator Considerations
Load Design: A new oscillator load configuration, shown in
Figure 7, has been found that eliminates start-up problems
sometimes encountered with 32kHz tuning fork crystals.
V_DD
C1
C2
X1
C3
OSC IN
OSC OUT
10
9
V_DD ²³
ICM7170
FIGURE 7. NEW OSCILLATOR CONFIGURATION
Two conditions must be met for best oscillator performance:
the capacitive load must be matched to both the inverter and
crystal to provide the ideal conditions for oscillation, and the
resonant frequency of the oscillator must be adjustable to
the desired frequency. In the original design (Figure 8),
these two goals were often at odds with each other; either
the oscillator was trimmed to frequency by detuning the load
circuit, or stability was increased at the expense of absolute
frequency accuracy.
Specification Numbe⁹r ICM7170_IM (IL) REV -
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