RS5C372A-E2-F Datasheet, PDF (30/57 Pages) RICOH electronics devices division – I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC

RS5C372A/B
1.2 Transmission System of I²C bus
1.2-1 Start and stop conditions
In I²C bus, SDA must be kept at a certain state while SCL is at the “H” state as shown below during data
transmission.
SCL
SDA
tSU;DAT
tHDL;DAT or tHDH;DAT
The SCL and SDA pins are at the “H” level when no data transmission is made. Changing the SDA from “H” to
“L” when the SCL and the SDA are “H” activates the start condition and access is started. Changing the SDA
from “L” to “H” when the SCL is “H” activates stop condition and accessing stopped. Generation of start and stop
conditions are always made by the master (see the figure below).
Start condition
SCL
Stop condition
SDA
tHD;STA
tSU;STO
1.2-2 Data transmission and its acknowledge
After start condition is entered, data is transmitted by 1byte (8bits). Any bytes of data may be serially
transmitted.
The receiving side will send an acknowledge signal to the transmission side each time 8bit data is transmitted.
The acknowledge signal is sent immediately after falling to “L” of SCL8bit clock pulses of data transmission, by
releasing the SDA by the transmission side that has asserted the bus at that time and by turning the SDA to “L”
by the receiving side. When transmission of 1byte data next to preceding 1byte of data is received, the receiving
side releases the SDA pin at falling edge of the SCL9bit of clock pulses or when the receiving side switches to
the transmission side it starts data transmission. When the master is the receiving side, it generates no
acknowledge signal after the last 1byte of data from the slave to tell the transmitter that data transmission has
completed when the slave side (transmission side) continues to release the SDA pin so that the master will be
able to generate stop condition.
SCL from the master
SDA from
the transmission side
SDA from
the receiving side
1
2
Start condition
8
9
Acknowledge signal
29