RV5C339A_03 Datasheet, PDF (15/46 Pages) RICOH electronics devices division – 3-WIRE SERIAL INTERFACE REAL-TIME CLOCK IC WITH VOLTAGE MONITORING FUNCTION

RV5C339A
2.2-7 WAFG and DAFG
Alarm_W Flag Bit and Alarm_D Flag Bit
WAFG, DAFG
Description
0
Indicating a mismatch between current time and preset alarm time
(Default setting)
1
Indicating a match between current time and preset alarm time
The WAFG and DAFG bits are valid only when the WALE and DALE bits have the setting of 1, which is caused
approximately 61µs after any match between current time and preset alarm time specified by the Alarm_W registers
and the Alarm_D registers. The WAFG and DAFG bits accept only the writing of 0, which disables (“H”) the
INTRA(or INTRB) pin until it is enabled (“L”) again at the next preset alarm time. Conversely, setting the WAFG
and DAFG bits to 1 causes no event. The WAFG and DAFG bits will have the reading of 0 when the alarm interrupt
circuit is disabled with the WALE and DALE bits set to 0.
Output Relationships Between the WAFG or DAFG Bit and INTRA, INTRB
Approx. 61µs
Approx. 61µs
Settings of WAFG (DAFG) bit
Output of INTRA (INTRB) pin
Writing of 0 to WAFG
(DAFG) bit
(Match between current time (Match between current time
and preset alarm time)
and preset alarm time)
Writing of 0 to WAFG
(DAFG) bit
(Match between current time
and preset alarm time)
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