R2023T-E2-F Datasheet, PDF (13/56 Pages) RICOH electronics devices division – 2-wire Serial Interface Real Time Clock IC

* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
REGISTER SETTINGS
• Control Register 1 (ADDRESS Eh)
D7
D6
D5
D4
D3
D2
D1
D0
WALE
DALE
12 /24 CLEN2 TEST
CT2
CT1
CT0
(For Writing)
WALE
DALE
12 /24 CLEN2 TEST
CT2
CT1
CT0
(For Reading)
0
0
0
0
0
0
0
0
Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from
0 volts.
(1) WALE, DALE
Alarm_W Enable Bit, Alarm_D Enable Bit
WALE, DALE
Description
0
Disabling the alarm interrupt circuit (under the control of the settings of the
Alarm_W registers and the Alarm_D registers).
1
Enabling the alarm interrupt circuit (under the control of the settings of the
Alarm_W registers and the Alarm_D registers)
(Default)
(2) 12 /24
12 /24-hour Mode Selection Bit
12 /24
Description
0
Selecting the 12-hour mode with a.m. and p.m. indications.
1
Selecting the 24-hour mode
Setting the 12 /24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.
(Default)
24-hour mode
00
01
02
03
04
05
06
07
08
09
10
11
12-hour mode
12 (AM12)
01 (AM 1)
02 (AM 2)
03 (AM 3)
04 (AM 4)
05 (AM 5)
06 (AM 6)
07 (AM 7)
08 (AM 8)
09 (AM 9)
10 (AM10)
11 (AM11)
Setting the 12 /24 bit should precede writing time data
24-hour mode
12
13
14
15
16
17
18
19
20
21
22
23
12-hour mode
32 (PM12)
21 (PM 1)
22 (PM 2)
23 (PM 3)
24 (PM 4)
25 (PM 5)
26 (PM 6)
27 (PM 7)
28 (PM 8)
29 (PM 9)
30 (PM10)
31 (PM11)
(3) CLEN2
32kHz Clock Output Bit 2
CLEN2
Description
0
Enabling the 32-kHz clock circuit
1
Disabling the 32-kHz clock circuit
(Default)
Setting the CLEN2 bit or the CLEN1 bit (D3 in the control register 2) to 0, and the CLKC pin to high specifies
generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT
pin. Conversely, setting both the CLEN1 and CLEN2 bit to 1 or CLKC pin to low specifies disabling (”L”) such
output.
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