DS9610B Datasheet, PDF (9/12 Pages) Richtek Technology Corporation – High Voltage Synchronous Rectified Buck MOSFET Driver for Notebook Computer

Application Information
Supply Voltage and Power On Reset
The RT9610B is designed to drive both high side and low
side N-MOSFETs through an externally input PWM control
signal. Connect 5V to VCC to power on the RT9610B. A
minimum 1μF ceramic capacitor is recommended to
bypass the supply voltage. Place the bypassing capacitor
physically near the IC. The power on reset (POR) circuit
monitors the supply voltage at the VCC pin. If VCC
exceeds the POR rising threshold voltage, the controller
resets and prepares for operation. UGATE and LGATE
are held low before VCC is above the POR rising threshold.
Enable and Disable
The RT9610B includes an EN pin for sequence control.
When the EN pin rises above the V_ENH trip point, the
RT9610B begins a new initialization and follows the PWM
command to control the UGATE and LGATE. When the
EN pin falls below the V_ENL trip point, the RT9610B shuts
down and keeps UGATE and LGATE low.
Three State PWM Input
After initialization, the PWM signal takes over the control.
The rising PWM signal first forces the LGATE signal low
and then allows the UGATE signal to go high right after a
non-overlapping time to avoid shoot through current. In
contrast, the falling PWM signal first forces UGATE to go
low. When the UGATE or PHASE signal reach a
predetermined low level, LGATE signal is then allowed to
go high.
Non-overlap Control
To prevent the overlap of the gate drives during the UGATE
pull low and the LGATE pull high, the non-overlap circuit
monitors the voltages at the PHASE node and high side
gate drive (UGATE-PHASE). When the PWM input signal
goes low, UGATE begins to pull low (after propagation
delay). Before LGATE can pull high, the non-overlap
protection circuit ensures that the monitored (UGATE-
PHASE) voltages have gone below 1.1V or phase voltage
is below 2V. Once the monitored voltages fall below the
threshold, LGATE begins to turn high. By waiting for the
voltages of the PHASE pin and high side gate drive to fall
RT9610B
below their threshold, the non-overlap protection circuit
ensures that UGATE is low before LGATE pulls high.
Also to prevent the overlap of the gate drives during LGATE
pull low and UGATE pull high, the non-overlap circuit
monitors the LGATE voltage. When LGATE go below 1.1V,
UGATE is allowed to go high.
Driving Power MOSFETs
The DC input impedance of the power MOSFET is
extremely high. The gate draws the current only for few
nano-amperes. Thus once the gate has been driven up to
“ON” level, the current could be negligible.
However, the capacitance at the gate to source terminal
should be considered. It requires relatively large currents
to drive the gate up and down rapidly. It is also required to
switch drain current on and off with the required speed.
The required gate drive currents are calculated as follows.
d1
V_IN
Cgd1
D1
s1
Cgs1
L
V_OUT
Igd1 ^Igs1
Ig1
g1 _g2
Ig2 ^Igd2
Igs2
Cgd2
d2
D2
Cgs2 s2
V_g1
V_PHASE +5V
GND
t
V_g2
5V
t
Figure1. Equivalent Circuit and Associated Waveforms
Copyright ©2016 Richtek Technology Corporation. All rights reserved.
DS9610B-07 August 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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