DS9610B Datasheet, PDF (11/12 Pages) Richtek Technology Corporation – High Voltage Synchronous Rectified Buck MOSFET Driver for Notebook Computer

Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature T_J(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
P_D(MAX) = (T_J(MAX) − T_A) / θ_JA
where T_J(MAX) is the maximum junction temperature, T_A is
the ambient temperature, and θ_JA is the junction-to-ambient
thermal resistance.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θ_JA, is highly package dependent. For a
WDFN-8L 2x2 package, the thermal resistance, θ_JA, is
120°C/W on a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. The maximum power
dissipation at T_A = 25°C can be calculated as below :
P_D(MAX) = (125°C − 25°C) / (120°C/W) = 0.833W for a
WDFN-8L 2X2 package
The maximum power dissipation depends on the operating
ambient temperature for the fixed T_J(MAX) and the thermal
resistance, θ_JA. The derating curves in Figure 3 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
RT9610B
0.9
Four-Layer PCB
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 3. Derating Curve of Maximum Power Dissipation
Layout Considerations
Figure 4 shows the schematic circuit of a synchronous
buck converter to implement the RT9610B.
L1
V_IN
12V
C1
V_CORE
C3
Q1
L2
Q2
C2
1
CB
BOOT _VCC 5
RT9610B
8 _UGATE
7 _PHASE
PHB83N03LT
2
PWM
6
EN
PHB95N03LT ⁴ _LGATE ^{GND 3}
5V
R1
C4
PWM
5V
Figure 4. Synchronous Buck Converter Circuit
When layout the PCB, it should be very careful. The power
circuit section is the most critical one. If not configured
properly, it will generate a large amount of EMI. The
junction of Q1, Q2, L2 should be very close.
Next, the trace from UGATE, and LGATE should also be
short to decrease the noise of the driver output signals.
PHASE signals from the junction of the power MOSFET,
carrying the large gate drive current pulses, should be as
heavy as the gate drive trace. The bypass capacitor C4
should be connected to GND directly. Furthermore, the
bootstrap capacitors (C_B) should always be placed as close
to the pins of the IC as possible.
Copyright ©2016 Richtek Technology Corporation. All rights reserved.
DS9610B-07 August 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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