RT8841 Datasheet, PDF (26/32 Pages) Richtek Technology Corporation – 4/3/2/1-Phase PWM Controller for High-Density Power Supply

RT8841
T2 = V_BOOT x C_SS/I_SS1
(2)
T3 is the dwelling time for V_OUT = V_BOOT. T3 = 800μs.
T4 is the soft start time from V_OUT = V_BOOT to V_OUT =
V_DAC.
T4 ~= |V_DAC − V_BOOT| x C_SS/I_SS1
(3)
T5 is the power good delay time, T5 ~= 1600μs.
V_TT
VCC12
VCC5
V_DAC
0.85V
9.6V
4.6V
SS
SSQ
PWRGD
T1
T2
T3
T4 T5
SS
SSQ
V_BOOT
Figure 5. Soft Start Waveforms
Dynamic VID
The RT8841 can accept VID input changing while the
controller is running. This allows the output voltage (V_OUT)
to change while the DC/DC converter is running and
supplying current to the load. This is commonly referred
to as VID on-the-fly (OTF). A VID OTF can occur under
either light or heavy load conditions. The CPU changes
the VID inputs in multiple steps from the start code to the
finish code. This change can be positive or negative.
Theoretically, V_OUT should follow V_DAC which is a staircase
waveform. In RT8841, as mentioned in soft start session,
V_DAC slew rate is limited by I_SS2/C_SS when PWRGD = H.
This slew rate limiter works as a low pass filter of V_DAC
and makes the bandwidth of V_DAC waveform finite. By
smoothening V_DAC staircase waveform, V_OUT will no longer
overshoot or undershoot. On the other hand, C_SS will
increase the settling time of V_OUT during VID OTF. In most
cases, 1nF to 30nF ceramic capacitor is suitable for C_SS.
Output Voltage Differential Sensing
The RT8841 uses differential sensing by a high gain low
offset ErrorAmp. The CPU voltage is sensed between the
FB and FBRTN pins. A resistor (R_FB) connects FB pin and
the positive remote sense pin of the CPU (V_CCP). FBRTN
pin connects to the negative remote sense pin of CPU
(V_CCN) directly. The ErrorAmp compares EAP (= V_DAC −
V_ADJ) with the V_FB to regulate the output voltage.
C2
C_FB
R1 ^C1
V_CCP
R_FB
(Positive remote
sense pin of CPU)
(Negative remote
sense pin of CPU)
V_CCN
R_ADJ
FB
I_OFSP
-
+
+-
EA
+
EAP
V_DAC
-
COMP
FBRTN
I_OFSN
ADJ
Figure 6. Circuit for V_OUT Differential Sensing and No
Load Offset
No-Load Offset
In Figure 6, I_OFSN or I_OFSP are used to generate no-load
offset. Either I_OFSN or I_OFSP is active during normal operation.
It should be noted that users can only enable one polarity
of no-load offset. Do not connect OFS pin to GND and to
V_CC5 at the same time. Connect a resistor from OFS pin
to GND to activate I_OFSN. I_OFSN flows through R_ADJ from
ADJ pin to GND. In this case, negative no-load offset voltage
(V_OFSN) is generated.
V_OFSN = I_OFSN x R_ADJ = 0.8 x R_ADJ/R_OFS
(4)
Connect a resistor from OFS pin to V_CC5 to activate I_OFSP.
I_OFSP flows through R_FB from the V_CCP to FB pin. In this
case, positive no-load offset voltage (V_OFSP) is generated.
When positive no-load offset is selected, the RT8841 will
generate another internal 8uA current source to eliminate
dead zone problem of droop function. This 8uA current
will be injected into ADJ resistors, producing a small initial
negative no-load offset. Therefore, when OFS pin is
connected to VCC5 through a resistor, the positive no-
load offset can be calculated as :
V_OFSP = I_OFSP ×R_FB − 8uA ×R_ADJ
=
6.4 × ^RFB
R_OFS
− 8uA ×R_ADJ
(5)
www.richtek.com
26
DS8841-01 April 2011