RT8862 Datasheet, PDF (21/29 Pages) Richtek Technology Corporation – Advanced 4/3/2/1-Phase PWM Controller with Embedded Drivers for CPU Core Power Supply

RT8862
V_TT
VCC12
VCC5
V_DAC
0.85V
9.6V
4.6V
SS
SSQ
PWRGD
T1
T2
T3
T4 T5
SS
SSQ
V_BOOT
Figure 5. Soft Start Waveforms
V_OUT will trace V_EAP which is equal to “V_SSQ − V_ADJ”.
V_ADJ is a small voltage signal which is proportional to
I_OUT. This voltage is used to generate loadline and will be
described later. T1 is the delay time from power_on_reset
state to the beginning of V_OUT rising.
T1 = 1600μs + 0.6V x C_SS / I_SS1
(1)
T2 is the soft start time from V_OUT = 0 to V_OUT = V_BOOT.
T2 = V_BOOT x C_SS / I_SS1
(2)
T3 is the dwelling time for V_OUT = V_BOOT. T3 = 800us.
T4 is the soft start time from V_OUT = V_BOOT to V_OUT = V_DAC.
T4 ~= |V_DAC - V_BOOT| x C_SS/I_SS1
(3)
T5 is the power good delay time, T5 ~= 1600μs.
Dynamic VID
The RT8862 can accept VID input changing while the
controller is running. This allows the output voltage (V_OUT)
to change while the DC/DC converter is running and
supplying current to the load. This is commonly referred
to as VID on-the-fly (OTF). A VID OTF can occur under
either light or heavy load conditions. The CPU changes
the VID inputs in multiple steps from the start code to the
finish code. This change can be positive or negative.
Theoretically, V_OUT should follow V_DAC which is a staircase
waveform. In RT8862, as mentioned in soft start session,
V_DAC slew rate is limited by I_SS2/C_SS when PWRGD = H.
This slew rate limiter works as a low pass filter of V_DAC
and makes the bandwidth of V_DAC waveform finite. By
smoothening V_DAC staircase waveform, V_OUT will no longer
overshoot or undershoot. On the other hand, C_SS will
increase the settling time of V_OUT during VID OTF. In most
cases, 1nF to 30nF ceramic capacitor is suitable for C_SS.
Output Voltage Differential Sensing
The RT8862 uses differential sensing by a high gain low
offset Error Amplifier. The CPU voltage is sensed between
the FB and FBRTN pins. A resistor (R_FB) connects FB pin
and the positive remote sense pin of the CPU (V_CCP).
FBRTN pin connects to the negative remote sense pin of
CPU (V_CCN) directly. The Error Amplifier compares EAP
(= V_DAC −V_ADJ) with the V_FB to regulate the output voltage.
No Load Offset
In Figure 6, I_OFSN or I_OFSP are used to generate no-load
offset. Either I_OFSN or I_OFSP is active during normal operation.
It should be noted that users can only enable one polarity
of no-load offset. Do not connect OFS pin to GND and to
V_CC5 at the same time. Connect a resistor from OFS pin
to GND to activate I_OFSN. I_OFSN flows through R_ADJ from
ADJ pin to GND. In this case, negative no-load offset voltage
(V_OFSN) is generated.
V_OFSN = I_OFSN x R_ADJ = 0.8 x R_ADJ/R_OFS
(4)
Connect a resistor from OFS pin to V_CC5 to activate I_OFSP.
I_OFSP flows through R_FB from the V_CCP to FB pin. In this
case, positive no-load offset voltage (V_OFSP) is generated.
When OFS pin is connected to VCC5 through a resistor,
the positive no-load offset can be calculated as :
V_OFSP
=
I_OFSP
× R_FB
=
6.4 ×
R_FB
R_OFS
(5)
The RT8862 provides wide range no-load positive offset
for over-clocking applications. The I_OFSP capability can
supply from 30μA to 640μA, which means in Equation
(5), R_OFS can range from 240kΩ to 10kΩ. Other resistances
of R_OFS exceeding this range can also provide no-load
positive offset but cannot be guaranteed by Equation (5).
DS8862-01 April 2011
www.richtek.com
21