RT9945 Datasheet, PDF (18/33 Pages) Richtek Technology Corporation – Power Management ICs for Handheld Device

RT9945
Application Information
I²C Start and Stop Conditions
Both DATA and CLK remain high when the bus is not busy.
A high-to-low transition of DATA, while CLK is high is defined
as the Start condition. A low-to-high transition of the data
line while CLK is high is defined as the Stop condition.
I²C Acknowledge
The number of data bytes between the start and stop
conditions for the Transmitter and Receiver are unlimited.
Each 8-bit byte is followed by an Acknowledge Bit. The
Acknowledge Bit is a high level signal put on DATA by the
transmitter during which time the master generates an extra
acknowledge related clock pulse. A slave receiver which
is addressed must generate an Acknowledge after each
byte it receives. Also a master receiver must generate an
Acknowledge after each byte it receives that has been
clocked out of the slave transmitter.
The device that Acknowledges must pull down the DATA
line during the acknowledge clock pulse, so that the DATA
line is stable low during the high period of the Acknowledge
clock pulse (set-up and hold times must also be met). A
master receiver must signal an end of data to the
transmitter by not generating an acknowledge signal on
the last byte that has been clocked out of the slave. In this
case the transmitter must leave DATA high to enable the
master to generate a stop condition.
I²C System Configuration
A device on the I2C Bus which generates a “message” is
called a “Transmitter” and a device that receives the
message is a “Receiver”. The device that controls the
message is the “Master” and the devices that are
controlled by the “Master” are called “Slaves”.
I²C Write Command.
The RT9945 writing address set 9C hex and write command
and data to set internal register.
TYPE I : Send the address and one command by I²C (Figure
3).
SCL
SDA
A6 A5
A0 W A 0
Dx4
01 or 10 or 11
START
Write command _Acknowledge
from the master. _{from the slave.}
START command from the master.
Dx0 A
Acknowledge _STOP
from the slave.
Figure 1. I²C Transmission Flow in the RT9945
VSYS
Processor
SCL
SDA
RT9945
SDO
Master
Slave
Figure 2. I²C Function Block in the RT9945
START
www.richtek.com
18
I²C Address
W
A6 A5 A4 A3 A2 A1 A0 0
The 2nd Word
9
0 0 1 D14 D13 D12 D11 D10
0 1 0 D24 D23 D22 D21 D20
0 1 1 D34 D33 D32 D31 D30
Figure 3. I²C One Command Flow in the RT9945
STOP
DS9945-01 April 2011