DS8813D Datasheet, PDF (18/23 Pages) Richtek Technology Corporation – Multi-Phase PWM Controller with PWM-VID Reference

RT8813D
Normal Mode
If the VID pin is driven by a PWM signal and switch Q1 is
disabled as shown in Figure 9, the V_VREFIN can be adjusted
from V_min to V_max, where V_min is the voltage at zero percent
PWM duty cycle and V_max is the voltage at one hundred
percent PWM duty cycle. The V_min and V_max can be set
by the following equations :
V_min
=
V_VREF

R_REF2
R_REF2  R_BOOT
  ^
R_REFADJ // (R_BOOT  R_REF2 )
R_REF1  R_REFADJ // (R_BOOT  R_REF2
)
V_max
=
V_VREF  _(RREF1
//
R_REF2
R_REFADJ )  R_BOOT
 R_REF2
By choosing R_REF1, R_REF2, and R_BOOT, the R_REFADJ can be
calculated by the following equation :
R_REFADJ

R_REF1  V_min
V_max  V_min
The relationship between VID duty and V_REFIN is shown in
Figure 9, and V_OUT can be set according to the calculation
below :
V_OUT = V_min  N V_STEP
where V_STEP is the resolution of each voltage step 1.
V_STEP
=
(V_max  V_min )
N_max
where N_max is the number of total available voltage steps
and N is the number of step at a specific V_OUT. The dynamic
voltage VID period (T_vid = T_u x N_max) is determined by the
unit pulse width (T_u) and the available step number (N_max).
The recommended T_u is 27ns.
V_REFIN
N = N_max
V_max
N=2
N=1
V_min
0
0.5
VID Duty
1
N=1
T_u
VID Input
N=2
T_vid = N_max x T_u
VID Input
Figure 11. PWM VID Analog Output
Copyright ©2016 Richtek Technology Corporation. All rights reserved.
www.richtek.com
18
VID Slew Rate Control
In RT8813D, the V_REFIN slew rate is proportional to PWM
VID duty, the rising time and falling time is the same
because the voltage of REFIN pin traveling is the same. In
normal mode, the V_REFIN slew rate SR can be estimated
by C_REFADJ or C_REFIN as the following equation :
When choose C_REFADJ :
SR =
(V_{REFIN_Final}  V_{REFIN_initial} ) 80%
2.2R_SRC_REFADJ
  RSR = (RREF1 // RREFADJ ) // (RBOOT +RREF2 )
When choose C_REFIN :
SR =
(V_{REFIN_Final}  V_{REFIN_initial} ) 80%
2.2R_SRC_REFIN
R_SR = R_REF1 //  R_REFADJ  R_BOOT  // R_REF2
The recommend SR is estimated by C_REFADJ.
Current Limit
The RT8813D provides cycle-by-cycle current limit control
by detecting the PHASE voltage drop across the low side
MOSFET when it is turned on. The current limit circuit
employs a unique “valley” current sensing algorithm as
shown in Figure 12. If the magnitude of the current sense
signal at PHASE is above the current limit threshold, the
PWM is not allowed to initiate a new cycle.
I_L
I_L,PEAK
I_LOAD
I_L,VALLEY
t
0
Figure 12. “Valley” Current Limit
In order to provide both good accuracy and a cost effective
solution, the RT8813D supports temperature compensated
MOSFET R_DS(ON) sensing.
In an over current condition, the current to the load exceeds
the average output inductor current. Thus, the output
voltage falls and eventually crosses the under voltage
protection threshold, inducing IC shutdown.
is a registered trademark of Richtek Technology Corporation.
DS8813D-00 September 2016