DS8813D Datasheet, PDF (16/23 Pages) Richtek Technology Corporation – Multi-Phase PWM Controller with PWM-VID Reference

RT8813D
The switching waveforms may be noisy and asynchronous
in light loading diode-emulation operation condition, but
this is a normal operating condition that results in high
light-load efficiency. Trade-off in DEM noise vs. light-load
efficiency is made by varying the inductor value. Generally,
low inductor values produce a broad high efficiency range
vs. load curve, while higher values result in higher full-
load efficiency (assuming that the coil resistance remains
fixed) and less output voltage ripple. The disadvantages
for using higher inductor values include larger physical
size and degraded load-transient response (especially at
low input voltage levels).
Forced-CCM Mode
The low noise, forced-CCM mode disables the zero-
crossing comparator, which controls the low side switch
on-time. This causes the low side gate drive waveform to
be the complement of the high side gate drive waveform.
This in turn causes the inductor current to reverse at light
loads as the PWM loop to maintain a duty ratio V_OUT/V_IN.
The benefit of forced-CCM mode is to keep the switching
frequency fairly constant.
Enable and Disable
The EN pin is a high impedance input that allows power
sequencing between the controller bias voltage and another
voltage rail. The RT8813D remains in shutdown if the EN
pin is lower than 800mV. When the EN voltage rises above
the 1.6V high level threshold, the RT8813D will begin a
new initialization and soft-start cycle.
Soft-Start
The RT8813D provides soft-start function. The soft-start
function is used to prevent large inrush current and output
voltage overshoot while the converter is being powered-
up. The soft-start function automatically begins once the
chip is enabled. There is a delay time around 250μs from
EN goes high to V_OUT begins to ramp-up.
An internal current source charges the internal soft-start
capacitor so that the internal soft-start voltage ramps up
linearly. The output voltage will track the internal soft-start
voltage during the soft-start interval. After the internal soft-
start voltage exceeds the REFIN voltage, the output voltage
no longer tracks the internal soft-start voltage but follows
the REFIN voltage. Therefore, the duty cycle of the UGATE
signal as well as the input current at power up are limited.
The soft-start process is finished until the single internal
SSOK go high and protection is not triggered. Figure 8
shows the internal soft-start sequence.
PVCC
EN
VOUT
Internal SS
Internal
SSOK
UGATE
VREFIN
Power On Reset (POR), UVLO
Power On Reset (POR) occurs when V_PVCC rises above
to approximately 4.1V (typical), the RT8813D will reset
the fault latch circuit and prepare for PWM operation. When
the V_PVCC is lower than 3.8V (typical), the Under Voltage
Lockout (UVLO) circuitry inhibits switching by keeping
UGATE and LGATE low.
LGATE
PGOOD
t_INIT
t_RAMP
Normal
Soft
Discharged
Figure 8. Internal Soft-Start Sequence
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DS8813D-00 September 2016