V Datasheet, PDF (12/14 Pages) Continental Device India Limited – SOT-23 Formed SMD Package

RT8288
reducing the SW trace area and keeping the main power
in a small loop will be helpful on EMI performance. For
detailed PCB layout guide, please refer to the section
Layout Considerations.
V_IN
R_EN*
C_IN
C_EN*
* : Optional
C_C
1 _VIN
BOOT ⁴
RT8288
5 _EN
SW ^{2, 3}
C_BOOT
L
C_S*
7
VCC
R_S*
FB ⁶
R_T
GND ^{8, 9 (Exposed Pad)}
V_OUT
C_OUT
R1
R2
Figure 5. Reference Circuit with Snubber and Enable Timing Control
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P_D(MAX) = (T_J(MAX) − T_A) / θ_JA
where T_J(MAX) is the maximum junction temperature, T_A is
the ambient temperature, and θ_JA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ_JA, is layout dependent. For
SOP-8 (Exposed Pad) package, the thermal resistance,
θ_JA, is 75°C/W on a standard JEDEC 51-7 four-layer
thermal test board. The maximum power dissipation at T_A
= 25°C can be calculated by the following formula :
P_D(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
The maximum power dissipation depends on the operating
ambient temperature for fixed T_J(MAX) and thermal
resistance, θ_JA. The derating curve in Figure 6 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
Four-Layer PCB
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum Power Dissipation
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DS8288-03 June 2012