V Datasheet, PDF (11/14 Pages) Continental Device India Limited – SOT-23 Formed SMD Package

RT8288
Input and Output Capacitors Selection
The input capacitance, C_IN, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
RMS current is given by :
I_RMS
=
I_OUT(MAX)
V_OUT
V_IN
V_IN
V_OUT
−1
This formula has a maximum at V_IN = 2V_OUT, where I_RMS =
I_OUT / 2. This simple worst case condition is commonly
used for design because even significant deviations do
not offer much relief.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design.
For the input capacitor, one 22μF low ESR ceramic
capacitors are recommended. For the recommended
capacitor, please refer to table 3 for more detail.
Location
C_IN
C_IN
C_OUT
C_OUT
C_OUT
C_OUT
Table 3. Suggested Capacitors for CIN and COUT
Component Supplier
MURATA
TDK
MURATA
TDK
MURATA
TDK
Part No.
GRM32ER71C226M
C3225X5R1C226M
GRM31CR60J476M
C3225X5R0J476M
GRM32ER71C226M
C3225X5R1C226M
Capacitance (μF)
22
22
47
47
22
22
Case Size
1210
1210
1206
1210
1210
1210
The selection of C_OUT is determined by the required ESR
to minimize voltage ripple.
Moreover, the amount of bulk capacitance is also a key
for C_OUT selection to ensure that the control loop is stable.
Loop stability can be checked by viewing the load transient
response.
The output ripple, ΔV_OUT, is determined by :
ΔV_OUT
≤
ΔI_L
⎡⎢⎣_{ESR +}
1
8fC_OUT
⎤
⎥⎦
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, V_IN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at V_IN large enough to damage the
part.
Thermal Shutdown
Thermal shutdown is implemented to prevent the chip from
operating at excessively high temperatures. When the
junction temperature is higher than 150°C, the chip will
shut down the switching operation. The chip will
automatically resume switching, once the junction
temperature cools down by approximately 30°C.
EMI Consideration
Since parasitic inductance and capacitance effects in PCB
circuitry would cause a spike voltage on SW pin when
high side MOSFET is turned-on/off, this spike voltage on
SW may impact on EMI performance in the system. In
order to enhance EMI performance, there are two methods
to suppress the spike voltage. One way is by placing an
R-C snubber (R_S*, C_S*) between SW and GND and locating
them as close as possible to the SW pin, as shown in
Figure 5. Another method is by adding a resistor in series
with the bootstrap capacitor, C_BOOT, but this method will
decrease the driving capability to the high side MOSFET.
It is strongly recommended to reserve the R-C snubber
during PCB layout for EMI improvement. Moreover,
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
DS8288-03 June 2012
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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