RT8082 Datasheet, PDF (12/14 Pages) Richtek Technology Corporation – 3A, 2MHz, Synchronous Step-Down Converter

RT8082
at the input, V_IN. This ringing can couple to the output
and be mistaken. A sudden inrush of current through the
long wires can potentially cause a voltage spike at V_IN
large enough to damage the part.
Two 10μF low ESR ceramic capacitors are recommended
for bypassing input and an additional 0.1μF is
recommended close to the IC input side for high frequency
filtering. The selection of C_OUT is determined by the
required ESR to minimize voltage ripple. Moreover, the
amount of bulk capacitance is also a key for C_OUT selection
to ensure that the control loop is stable. Loop stability
can be checked by viewing the load transient response.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant
frequency architectures by preventing sub harmonic
oscillations at duty cycles greater than 50%. It is
accomplished internally by adding a compensating ramp
to the inductor current signal. Normally, the maximum
inductor peak current is reduced when slope compensation
is added. For the RT8082, a separate inductor current
signal is used to monitor over current condition, so this
keeps the maximum output current relatively constant
regardless of duty cycle.
Under Output Voltage Protection (Hiccup Mode)
A Hiccup Mode of Under Voltage Protection (UVP) function
is provided for the IC. When the FB voltage drops below
half of the feedback reference voltage, V_REF, and the peak
inductor current reaches the OCP threshold. The UVP
function will be triggered to auto soft-start the power stage
continuously until this event is cleared. The Hiccup Mode
UVP reduces input current in short-circuit conditions and
it will not be triggered during soft-start process.
Under Voltage Lockout Threshold
The IC features input Under Voltage Lockout protection
(UVLO). If the input voltage exceeds the UVLO rising
threshold voltage (2.45V typ.), the converter will reset and
prepare the PWM for operation. If the input voltage falls
below the UVLO falling threshold voltage (2.25V typ.)
during normal operation, the device will stop switching.
The UVLO rising and falling threshold voltage has a
hysteresis (0.2V typ.) to prevent noise from causing reset.
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
Thermal Shutdown
The device implements an internal thermal shutdown
function when the junction temperature exceeds 160°C.
The thermal shutdown disables the device until the junction
temperature drops below the hysteresis (20°C typ.). Then,
the device is re-enabled and automatically reinstates the
power up sequence.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P_D(MAX) = (T_J(MAX) − T_A) / θ_JA
where T_J(MAX) is the maximum junction temperature, T_A is
the ambient temperature, and θ_JA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ_JA, is layout dependent. For
WDFN-12E 3x3, the thermal resistance, θ_JA, is 60°C/W
on a standard JEDEC 51-7 four-layer thermal test board.
The maximum power dissipation at T_A = 25°C can be
calculated by the following formula :
P_D(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for
WDFN-12E 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T_J(MAX) and thermal
resistance, θ_JA. The derating curve in Figure 2 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
is a registered trademark of Richtek Technology Corporation.
DS8082-00 November 2012