RFSA2624 Datasheet, PDF (5/9 Pages) RF Micro Devices – SERIAL CONTROLLED DIGITAL STEP ATTENUATOR

RFSA2624
Truth Table
Control Bit
C16
C8
C4
C2
C1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
0
0
0
0
Note: C 0.5=D0, C1=D1, ... C16=D5 (for the purpose of the example below)
C0.5
1
0
1
1
1
1
1
0
Relative Gain
Setting
Max gain
-0.5 dB
-1 dB
-2 dB
-4 dB
-8 dB
-16 dB
-31.5 dB
t4
CLK
DATA
t7
LE
DOUT
Serial Port Interface
SPI Timing Diagram
t6
t1
t2
t3
t5
t8
Programming example – 6-bit
CLK
DATA
MSB
LSB
D5
D4 D3
D2
D1 D0
LE
t9
t10
SPI Timing Diagram Specifications
Parameter
t1
Limit
25
Unit
MHz max
Comment
CLK Frequency
t2
20
ns min
CLK High
t3
20
ns min
CLK Low
t4
5
ns min
DATA to CLK Setup Time
t5
5
ns min
DATA to CLK Hold Time
t6
30
ns min
Data Valid
t7
5
ns min
LE to CLK Setup Time
t8
5
ns min
CLK to LE Setup Time
t9
10
ns min
LE Pulse Width
t10
20
ns min
Output Set
LOGIC Voltage Levels
State
Logic
Low
0V to 0.8V
High
2.0V to 5.0V
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