RX5003 Datasheet, PDF (5/11 Pages) RF Monolithics, Inc – 303.825 MHz Hybrid Receiver

A n te n n a
R F IO
20
ESD
C hoke
SAW
C R F ilte r
R X 5 0 0 0 S e r ie s A S H R e c e iv e r B lo c k D ia g r a m
C N TR L1
C N TR L0
17
18
B ia s C o n tr o l
P ow er
D ow n
C o n tro l
Log
V C C 1 : P in 2
V C C 2 : P in 1 6
G N D 1 : P in 1
G N D 2 : P in 1 0
G N D 3 : P in 1 9
N C : P in 8
R R E F : P in 1 1
C M P IN : P in 6
R FA1
SAW
D e la y L in e
A G C S et
G a in S e le c t
R FA2
D e te c to r
L o w -P a s s
F ilte r
BB
LP FA D J 9
R _LPF
P u ls e G e n e r a to r
& R F A m p B ia s
P R A TE 14
1 5 P W ID T H
R _PR
R _PW
AG C
C o n tro l
AG CCAP 3
C _AGC
A G C R eset
BBO UT
P eak
R ef
5
6
C _BBO
D e te c to r
PKDET 4
C _PKD
DS2
d B B e lo w
P e a k T h ld
AND
7
R XD ATA
AG C
DS1
R ef
T h ld
T h r e s h o ld
C o n tro l
TH LD 1
13
R _TH1
11 12
R _TH2
R _REF
TH LD 2
Figure 2
the start of the next RFA1 ON sequence should be set to sample
the narrowest RF data pulse at least 10 times. Otherwise, significant
edge jitter will be added to the detected data pulse.
RX5000 Series ASH Receiver Block Diagram
Figure 2 is the general block diagram of the RX5000 series ASH
receiver. Please refer to Figure 2 for the following discussions.
Antenna Port
The only external RF components needed for the receiver are the
antenna and its matching components. Antennas presenting an im-
pedance in the range of 35 to 72 ohms resistive can be satisfactorily
matched to the RFIO pin with a series matching coil and a shunt
matching/ESD protection coil. Other antenna impedances can be
matched using two or three components. For some impedances,
two inductors and a capacitor will be required. A DC path from RFIO
to ground is required for ESD protection.
Receiver Chain
The output of the SAW filter drives amplifier RFA1. This amplifier in-
cludes provisions for detecting the onset of saturation (AGC Set),
and for switching between 35 dB of gain and 5 dB of gain (Gain Se-
lect). AGC Set is an input to the AGC Control function, and Gain Se-
lect is the AGC Control function output. ON/OFF control to RFA1
(and RFA2) is generated by the Pulse Generator & RF Amp Bias
function. The output of RFA1 drives the SAW delay line, which has
a nominal delay of 0.5 µs.
The second amplifier, RFA2, provides 51 dB of gain below satura-
tion. The output of RFA2 drives a full-wave detector with 19 dB of
threshold gain. The onset of saturation in each section of RFA2 is
detected and summed to provide a logarithmic response. This is
added to the output of the full-wave detector to produce an overall
detector response that is square law for low signal levels, and tran-
sitions into a log response for high signal levels. This combination
provides excellent threshold sensitivity and more than 70 dB of
detector dynamic range. In combination with the 30 dB of AGC
range in RFA1, more than 100 dB of receiver dynamic range is
achieved.
The detector output drives a gyrator filter. The filter provides a
three-pole, 0.05 degree equiripple low-pass response with excellent
group delay flatness and minimal pulse ringing. The 3 dB bandwidth
of the filter can be set from 4.5 kHz to 1.8 MHz with an external re-
sistor.
The filter is followed by a base-band amplifier which boosts the de-
tected signal to the BBOUT pin. When the receiver RF amplifiers
are operating at a 50%-50% duty cycle, the BBOUT signal changes
about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV.
For lower duty cycles, the mV/dB slope and peak-to-peak signal
level are proportionately less. The detected signal is riding on a
1.1 Vdc level that varies somewhat with supply voltage, tempera-
ture, etc. BBOUT is coupled to the CMPIN pin or to an external data
recovery process (DSP, etc.) by a series capacitor. The correct
value of the series capacitor depends on data rate, data run length,
and other factors as discussed in the ASH Transceiver Designer’s
Guide.
When an external data recovery process is used with AGC, BBOUT
must be coupled to the external data recovery process and CMPIN
by separate series coupling capacitors. The AGC reset function is
driven by the signal applied to CMPIN.
When the receiver is placed in the power-down (sleep) mode, the
output impedance of BBOUT becomes very high. This feature helps
preserve the charge on the coupling capacitor to minimize data
slicer stabilization time when the receiver switches out of the sleep
mode.
Data Slicers
The CMPIN pin drives two data slicers, which convert the analog
signal from BBOUT back into a digital stream. The best data slicer
choice depends on the system operating parameters. Data slicer
DS1 is a capacitively-coupled comparator with provisions for an ad-
justable threshold. DS1 provides the best performance at low
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