RX5003 Datasheet, PDF (10/11 Pages) RF Monolithics, Inc – 303.825 MHz Hybrid Receiver

Pin
Name
Description
This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R_LPF between this
pin and ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth f_LPF from
4.5 kHz to 1.8 MHz. The resistor value is determined by:
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LPFADJ
R_LPF = 1445/ f_LPF, where R_LPF is in kilohms, and f_LPF is in kHz
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between f_LPF
and 1.3* f_LPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree
equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter
bandwidth setting.
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GND2
GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.
RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground.
A ±1% resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and
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RREF
this node to less than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF
through resistor values less that 1.5 K, their node capacitance must be added to the RREF node capacitance and
the total should not exceed 5 pF.
THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 K resistor
R_TH2 between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak de-
tector value (increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB
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THLD2
below peak, or 60 mV for a 50%-50% RF amplifier duty cycle. The value of the THLD2 resistor is given by:
R_TH2 = 1.67*V, where R_TH2 is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the
dB-below-peak data slicer operation.
The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor R_TH1 to RREF. The thresh-
old is increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold.
The value of the resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the accept-
able range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:
R_TH1 = 1.11*V, where R_TH1 is in kilohms and the threshold V is in mV
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THLD1
For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a
THLD1 range of 0 to 90 mV. The resistor value is given by:
R_TH1 = 2.22*V, where R_TH1 is in kilohms and the threshold V is in mV
A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required
for proper AGC operation.
The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON
pulse to the first RF amplifier t_PRI is set by a resistor R_PR between this pin and ground. The interval t_PRI can be ad-
justed between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of R_PR is given by:
R_PR = 404* t_PRI + 10.5, where t_PRI is in µs, and R_PR is in kilohms
A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF
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PRATE
amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period
t_PRC from start-to-start of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1
to 1.1 µs using a resistor of 11 K to 220 K. In this case the value of R_PR is given by:
R_PR = 198* t_PRC - 8.51, where t_PRC is in µs and R_PR is in kilohms
A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for
additional amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and
this pin to less than 5 pF to maintain stability.
The PWIDTH pin sets the width of the ON pulse to the first RF amplifier t_PW1 with a resistor R_PW to ground (the ON
pulse width to the second RF amplifier t_PW2 is set at 1.1 times the pulse width to the first RF amplifier). The ON
pulse width t_PW1 can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The
value of R_PW is given by:
R_PW = 404* t_PW1 - 18.6, where t_PW1 is in µs and R_PW is in kilohms
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PWIDTH _{A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifi-}
ers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier
ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance
between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation
with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the
sleep mode.
VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capaci-
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VCC2
tor, which may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic ca-
pacitor.
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