R1QBA4436RBG Datasheet, PDF (9/37 Pages) Renesas Technology Corp – 144-Mbit DDRII+ SRAM 2-word Burst

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144M
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
General Description
Power-up and Initialization Sequence
- V_DD must be stable before K, /K clocks are applied.
- Recommended voltage application sequence : V_SS ĺ V_DD ĺ V_DDQ & V_REF ĺ V_IN. (0 V to V_DD, V_DDQ < 200 ms)
- Apply V_REF after V_DDQ or at the same time as V_DDQ.
- Then execute either one of the following three sequences.
1. Single Clock Mode (C and /C tied high)
- Drive /DOFF high (/DOFF can be tied high from the start).
- Then provide stable clocks (K, /K) for at least 20 us.
1. Single clock mode (C and /C pins fixed High)
Status
V_DD
V_DDQ
V_REF
/DOFF
K, /K
Power Up &
Unstable Stage
NOP &
Set-up Stage
Fix High (=Vddq)
SET-UP Cycle
Normal
Operation
2. Double Clock Mode (C and /C control outputs) (II series only)
- Drive /DOFF high (/DOFF can be tied high from the start)
- Then provide stable clocks (K, /K , C, /C) for at least 20 us.
2. Double clock mode
Status
V_DD
V_DDQ
V_REF
/DOFF
K, /K
Power Up &
Unstable Stage
NOP &
Set-up Stage
Fix High (=Vddq)
SET-UP Cycle
C, /C
Normal
Operation
3. DLL/PLL Off Mode (/DOFF tied low)
- In the "NOP and setup stage", provide stable clocks (K, /K) for at least 20 us.
Rev. 0.11b : 2012.06.05
R10DS0189EJ0011
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