R1Q4A3636B Datasheet, PDF (9/26 Pages) Renesas Technology Corp – 36-Mbit DDRII SRAM 2-word Burst

R1Q4A3636B/R1Q4A3618B
Byte Write Truth Table (x18)
Operation
K
/K
/BW0
/BW1
Write D0 to D17
↑

L
L

↑
L
L
Write D0 to D8
↑

L
H

↑
L
H
Write D9 to D17
↑

H
L

↑
H
L
Write nothing
↑

H
H

↑
H
H
Notes: 1. H: high level, L: low level, ↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
Bus Cycle State Diagram
/LD = H & Count = 2
/LD = H
NOP
R-/W = L
/LD = L
&
Count = 2
Write Double
Count
= Count + 2
/LD = L
Load New
Address
Count = 0
Supply
voltage
provided
Power
Up
R-/W = H
/LD = L
&
Count = 2
Read Double
Count
= Count + 2
/LD = H & Count = 2
Notes: 1. SA0 is internally advanced in accordance with the burst order table. Bus cycle is terminated at the end of this
sequence (burst count = 2).
2. State machine control timing sequence is controlled by K.
REJ03C0343-0003 Rev.0.03 Apr.11, 2008
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