R1EX24128BSAS0G Datasheet, PDF (9/18 Pages) Renesas Technology Corp – Two-wire serial interface 128k EEPROM

R1EX24128BSAS0G/R1EX24128BTAS0G
Write Operations(WP=Low)
Byte Write: (Write operation during WP=Low status)
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment
"0" at the ninth clock cycle. After these, the 128kbit EEPROM receives 2 sequence 8-bit memory address words. Upon
receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data.
After receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the
EEPROM enters an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the
write cycle. The EEPROM returns to a standby mode after completion of the write cycle.
Byte Write Operation
WP
128k
Start
Device
address
1010
1st Memory
address (n)
W
ACK
R/W
Note: 1. Don't care bit
2nd Memory
address (n)
Write data (n)
ACK
ACK
ACK _Stop
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 64 bytes to be written in a
single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The
page write is initiated by a start condition, device address word, memory address(n) and write data (Dn) with every
ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data
(Dn+1) instead of receiving a stop condition. The a0 to a5 address bits are automatically incremented upon receiving
write data (Dn+1). The EEPROM can continue to receive write data up to 64 bytes. If the a0 to a5 address bits reaches
the last address of the page, the a0 to a5 address bits will roll over to the first address of the same page and previous
write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters
internally-timed write cycle.
Page Write Operation
WP
128k
Start
Device
address
1010
1st Memory
address (n)
W
ACK
R/W
Note: 1. Don't care bit
2nd Memory
address (n)
Write data (n) Write data (n+m)
ACK
ACK
ACK
ACK
Stop
R10DS0109EJ0200 Rev.2.00
Feb. 18, 2013
Page 9 of 16