R1EX24128BSAS0G Datasheet, PDF (14/18 Pages) Renesas Technology Corp – Two-wire serial interface 128k EEPROM

R1EX24128BSAS0G/R1EX24128BTAS0G
Notes
Data Protection at V_CC On/Off
When V_CC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a
trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this
EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset
function to operate correctly.
 SCL and SDA should be fixed to V_CC or V_SS during V_CC on/off. Low to high or high to low transition during V_CC
on/off may cause the trigger for the unintentional programming.
 V_CC should be turned off after the EEPROM is placed in a standby state.
 V_CC should be turned on from the ground level(V_SS) in order for the EEPROM not to enter the unintentional
programming mode.
 V_CC turn on rate should be slower than 2 s/V.
Noise Suppression Time
This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 100 ns. Be
careful not to allow noise of width more than 100 ns.
Power Source Noise Countermeasures
In order to suppress power-source-noise which causes malfunction of the device, it is recommended to put 0.1uF
bypass-capacitor (such as a monolithic ceramic capacitor which has good high-frequency characteristics) between V_CC
and V_SS, and shorten the wiring length between the capacitor and V_CC/V_SS terminals as much as possible.
Device Address Input and Write Protect Input
These pins are used by open status because they are pulled down in the device. Please notice
R10DS0109EJ0200 Rev.2.00
Feb. 18, 2013
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