HD74LV163A_15 Datasheet, PDF (9/17 Pages) Renesas Technology Corp – Synchronous 4-bit Binary Counter (Synchronous Clear)

HD74LV163A
Switching Characteristics
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Hold time
Pulse width
Symbol
fmax
t_PLH/t_PHL
t_PLH/t_PHL
Count mode
t_PLH/t_PHL
Load mode
t_PLH/t_PHL
t_su
t_h
t_w
Ta = 25°C
Ta = –40 to 85°C
Test
V_CC = 2.5 ± 0.2 V
FROM TO
Min Typ Max Min
Max
Unit Conditions (Input) (Output)
50 90 — 40
30 60 — 25
— 11.1 16.2 1.0
— 14.3 19.2 1.0
— 11.5 17.0 1.0
— 14.7 20.0 1.0
— 13.8 20.6 1.0
— 17.0 23.6 1.0
— 10.3 15.7 1.0
— 14.0 18.7 1.0
7.5 — — 8.5
—
—
19.5
22.5
20.5
23.5
24.5
27.5
19.0
22.0
—
MHz
ns
ns
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
CLK
Q
CLK
Carry
CLK
Carry
ENT
Carry
Data before CLK ↑
10.0 — — 11.5 —
LOAD before CLK ↑
9.5 — — 11.0 —
ENT, ENP before
CLK ↑
6.0 — — 6.0
—
CLR before CLK ↑
1.5 — — 1.5
—
ns
1.5 — — 1.5
—
CLR after CLK ↑
7.0 — — 7.0
—
ns
CLK H or L
Rev.5.00 Jun. 04, 2004 page 7 of 14