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HD74LV125A_15 Datasheet, PDF (9/12 Pages) Renesas Technology Corp – Quad. Bus Buffer Gates with 3-state Outputs | |||
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HD74LV125A
⢠Waveform â 1
Input A
tr
10 %
90 %
50 %VCC
tPLH
tf
90 %
50 %VCC
10 %
tPHL
Output Y
50 %VCC
50 %VCC
VCC
GND
VOH
VOL
⢠Waveform â 2
tf
90 %
Input OE 50 %VCC
10 %
tZL
Waveform â A
Waveform â B
50 %VCC
tZH
50 %VCC
tr
10 %
90 %
50 %VCC
tLZ
VOL + 0.3 V
tHZ
VOH â 0.3 V
VCC
GND
VCC
VOL
VOH
GND
Notes: 1. tr ⤠3 ns, tf ⤠3 ns
2. Input waveform: PRR ⤠1 MHz, duty cycle 50%
3. WaveformâA is for an output with internal conditions such that the output is low except when
disabled by the output control.
4. WaveformâB is for an output with internal conditions such that the output is high except when
disabled by the output control.
Rev.3.00 Jun. 03, 2004 page 7 of 9
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