HD74HC595_15 Datasheet, PDF (9/13 Pages) Renesas Technology Corp – 8-bit Shift Register/Latch (with 3-state outputs)

HD74HC595
Test Circuit
VCC
Input
Pulse Generator
Zout = 50 Ω
Input
Pulse Generator
Zout = 50 Ω
VCC
Output
G Q_A to Q_H
or
RCK _QH'
SER
SCK
SCLR
1 k Ω _S1
C_L =
50 pF
OPEN
GND
V_CC
TEST
t_PLH / t _PHL
t_ZH/ t _HZ
t_ZL / t _LZ
S1
OPEN
GND
V_CC
Note : 1. C_L includes probe and jig capacitance.
Waveforms
• Waveform – 1 (SCK to QH')
tr
tf
90 %
V_CC
Input SCK
50 % 50 %
50 %
10 %
tw(H)
10 %
tw(L)
0V
t_PLH
t_PHL
90 %
90 %
V_OH
Output QH'
50 %
50 %
10 %
10 %
V_OL
t_TLH
t_THL
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, t_r ≤ 6 ns, t_f ≤ 6 ns
• Waveform – 2 (RCK to Q)
t_r
90 %
V_CC
Input RCK
50 %
10 %
0V
t_PLH/t_PHL
Output
90 %
90 %
V_OH
QA to QH
10 %
50 %
10 %
V_OL
t_TLH/t_THL
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, t_r ≤ 6 ns, t_f ≤ 6 ns
Rev.2.00 Mar 30, 2006 page 7 of 10