HD74HC190 Datasheet, PDF (9/13 Pages) Hitachi Semiconductor – Synchronous Up/Down Decade,4-bit Binary Counter(Single Clock Line)

HD74HC190, HD74HC191
• Waveform – 2
Load
tf
90%
50%
10%
tf
90%
50%
10%
V_CC
0V
Data
(A to D)
90%
10%
tr _tPLH
90%
10%
tf
tPHL
50%
tPLH
50%
tPHL
V_CC
0V
Output Q
(Corresponding to data input)
50%
10%
90%
tTLH
90%
50% 50%
10% 10%
90%
tTHL
tTLH
90%
VOH
50%
10% _VOL
tTHL
Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, t_r ≤ 6 ns, t_f ≤ 6 ns
2. Conditions on other inputs are Vcc.
• Waveform – 3
Load
Down / Up
Clock
V_CC
0V
t_r
t_f
90 %
V_CC
50 % 50 %
10 %
10 %
0V
t_f
t_r
90 %
90 %
V_CC
50 %
50 %
10 %
10 %
0V
G
Ripple / Clock
Max / Min
V_CC
0V
t_PHL
t_PHL
t_PHL
t_PLH
90 %
50 % 50 %
10 %
90 %
10 %
t_THL
t_TLH
90 %
50 % 50 %
10 %
90 %
10 %
t
t_THL
PLH
t_PHL^tTLH
50 %
10 %
90 %
50 %
10 %
V_OH
V_OL
V_OH
V_OL
t_TLH
t_THL
Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, t_r ≤ 6 ns, t _f ≤ 6 ns
2. All data inputs are GND.
Rev.3.00, Jan 31, 2006 page 9 of 12