HD74HC190 Datasheet, PDF (10/13 Pages) Hitachi Semiconductor – Synchronous Up/Down Decade,4-bit Binary Counter(Single Clock Line)

HD74HC190, HD74HC191
• Waveform – 4
Load
Data
(A to D)
Down / Up
tf
tr
Clock
Q
90%
10%
90%
50%
tPLH
50%
10%
90%
50%
tPHL
90%
50%
10%
tTLH
tTHL
Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, t_r ≤ 6 ns, t_f ≤ 6 ns
2. Enable = GND
V_CC
0V
V_CC
0V
V_CC
0V
V_CC
0V
VOH
VOL
• Waveform – 5
V_CC
Load
0V
V_CC
Data
0V
(A to D)
V_CC
0V
V_CC
Down / Up
0V
Clock
50 %
50 %
V_CC
50 %
50 %
t_PLH
t_PHL
t_PLH
t_PHL
0V
Max / Min
50 %
10 %
90 % 90 %
50 %
10 %
t_TLH
t_THL
50 %
10 %
90 % 90 %
50 %
10 %
V_OH
V_OL
t_TLH
t_THL
Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, t_r ≤ 6 ns, t_f ≤ 6 ns
2. Enable = GND
Rev.3.00, Jan 31, 2006 page 10 of 12