H8SX1582 Datasheet, PDF (87/796 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1500 Series

Section 2 CPU
Instruction Size
BISTZ
B
BFLD
B
BFST
B
Function
∼ Z → (<bit-No.> of <EAd>)
Transfers the inverse of the zero flag value to a specified bit in the
contents of a memory location. The bit number is specified by 3-bit
immediate data.
(EAs) (bit field) → Rd
Transfers a specified bit field in memory location contents to the lower bits
of a specified general register.
Rs → (EAd) (bit field)
Transfers the lower bits of a specified general register to a specified bit
field in memory location contents.
Table 2.10 Branch Instructions
Instruction
BRA/BS
BRA/BC
BSR/BS
BSR/BC
Size
B
B
Bcc

BRA/S

JMP

BSR

JSR

RTS

RTS/L

Function
Tests a specified bit in memory location contents. If the specified
condition is satisfied, execution branches to a specified address.
Tests a specified bit in memory location contents. If the specified
condition is satisfied, execution branches to a subroutine at a specified
address.
Branches to a specified address if the specified condition is satisfied.
Branches unconditionally to a specified address after executing the next
instruction. The next instruction should be a 1-word instruction except for
the block transfer and branch instructions.
Branches unconditionally to a specified address.
Branches to a subroutine at a specified address.
Branches to a subroutine at a specified address.
Returns from a subroutine.
Returns from a subroutine, restoring data from the stack to multiple
general registers.
Rev. 2.00 Mar. 15, 2006 Page 49 of 754
REJ09B0199-0200