H8SX1582 Datasheet, PDF (605/796 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1500 Series

Section 17 Flash Memory (0.18-µm F-ZTAT Version)
(b) Programming
FPFR indicates the return value of the programming result.
Bit
7
6
5
4
3
2
1
0
Bit Name
—
MD
EE
FK
—
WD
WA
SF
Initial
Bit
Bit Name Value R/W Description
7



Unused
Returns 0.
6
MD

R/W Programming Mode Related Setting Error Detect
Detects the error protection state and returns the result.
When the error protection state is entered, this bit is set
to 1. Whether the error protection state is entered or not
can be confirmed with the FLER bit in FCCS. For
conditions to enter the error protection state, see section
17.9.3, Error Protection.
0: Normal operation (FLER = 0)
1: Error protection state, and programming cannot be
performed (FLER = 1)
5
EE

R/W Programming Execution Error Detect
Writes 1 to this bit when the specified data could not be
written because the user MAT was not erased. If this bit
is set to 1, there is a high possibility that the user MAT
has been written to partially. In this case, after removing
the error factor, erase the user MAT. If FMATS is set to
H'AA and the user boot MAT is selected, an error occurs
when programming is performed. In this case, both the
user MAT and user boot MAT have not been written to.
Programming the user boot MAT should be performed in
boot mode or programmer mode.
0: Programming has ended normally
1: Programming has ended abnormally (programming
result is not guaranteed)
Rev. 2.00 Mar. 15, 2006 Page 567 of 754
REJ09B0199-0200