H836049 Datasheet, PDF (86/562 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Tiny Series

Section 3 Exception Handling
Initial
Bit
Bit Name Value R/W Description
0
IWPF0 0
R/W WKP0 Interrupt Request Flag
[Setting condition]
When WKP0 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IWPF0 is cleared by writing 0.
3.3 Reset Exception Handling
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output
stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock
cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts
reset exception handling. The reset exception handling sequence is shown in figure 3.1. However,
for the reset exception handling sequence of the product with on-chip power-on reset circuit, refer
to section 20, Power-On Reset and Low-Voltage Detection Circuits (Optional).
The reset exception handling sequence is as follows:
1. Set the I bit in the condition code register (CCR) to 1.
2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the
data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.
Rev. 3.00 Mar. 15, 2006 Page 54 of 526
REJ09B0060-0300