H836049 Datasheet, PDF (316/562 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Tiny Series

Section 14 Timer Z
5. Contention between GR Read and Input Capture: If an input capture signal is generated in the
T₁ state of a GR read cycle, the data that is read will be transferred before input capture
transfer. Figure 14.56 shows the timing in this case.
GR read cycle
T₁
T₂
φ
Internal read
signal
Input capture
signal
GR address
GR
X
M
Internal data
bus
X
Figure 14.56 Contention between GR Read and Input Capture
Rev. 3.00 Mar. 15, 2006 Page 284 of 526
REJ09B0060-0300