H83802_10 Datasheet, PDF (85/546 Pages) Renesas Technology Corp – Renesas 8-Bit Single-Chip Microcomputer H8 Family / H8/300L Super Low Power Series

Figure 2.11 shows the instruction formats of block data transfer instructions.
Section 2 CPU
15
87
0
op
op
Legend:
op: Operation field
Figure 2.11 Instruction Format of Block Data Transfer Instructions
2.6 Addressing Modes and Effective Address
2.6.1 Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Table 2.11 Addressing Modes
No.
Addressing Mode
1
Register direct
2
Register indirect
3
Register indirect with displacement
4
Register indirect with post-increment
Register indirect with pre-decrement
5
Absolute address
6
Immediate
7
Program-counter relative
8
Memory indirect
Symbol
Rn
@Rn
@(d:16,Rn)
@Rn+
@–Rn
@aa:8/@aa:16
#xx:8/#xx:16
@(d:8,PC)
@@aa:8
Register Direct—Rn
The register field of the instruction specifies an 8- or 16-bit general register containing the
operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
Rev. 7.00 Mar. 08, 2010 Page 53 of 510
REJ09B0024-0700