RMQSKA3636DGBA_15 Datasheet, PDF (8/31 Pages) Renesas Technology Corp – 36-Mbit QDR™ II+ SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

RMQSKA3636DGBA, RMQSKA3618DGBA
Block Diagram
[RMQSKA3636DGBA]
18
Address
/R
/W
K
/K
Address
Registry
and
Logic
/W
4
/BWx
D ³⁶
(Data in)
/R
K
/K
72
Data
Registry 72
and
Logic
K
18
Memory
Array
Preliminary Datasheet
ZQ
72
144
72
K
K,/K
Q
(Data out)
36
2
CQ
/CQ
[RMQSKA3618DGBA]
19
Address
/R
/W
K
/K
Address
Registry
and
Logic
/W
2
/BWx
D ¹⁸
(Data in)
/R
K
/K
36
Data
Registry 36
and
Logic
K
19
Memory
Array
ZQ
36
72
36
K
K,/K
Q
(Data out)
18
2
CQ
/CQ
R10DS0239EJ0002 Rev.0.02
Dec. 01, 2014
Page 8 of 30