RMQSKA3636DGBA_15 Datasheet, PDF (17/31 Pages) Renesas Technology Corp – 36-Mbit QDR™ II+ SRAM 4-word Burst Architecture (2.0 Cycle Read latency) with ODT

RMQSKA3636DGBA, RMQSKA3618DGBA
Thermal Resistance
Preliminary Datasheet
Parameter
Junction to Ambient
Junction to Case
Symbol
θJA
θJC
Airflow
1 m/s
-
Typ
Unit
Test condition
Notes
13
°C/W EIA/JEDEC JESD51
1
6.3
Notes:
1. These parameters are calculated under the condition. These are reference values.
2. Tj = Ta + θ_JA × Pd
Tj = Tc + θ_JC × Pd
where
Tj : junction temperature when the device has achieved a steady-state after application of Pd (°C)
Ta :ambient temperature (°C)
Tc :temperature of external surface of the package or case (°C)
θ_JA :thermal resistance from junction-to-ambient (°C/W)
θ_JC :thermal resistance from junction-to-case (package) (°C/W)
Pd :power dissipation that produced change in junction temperature (W) (cf.JESD51-2A)
Capacitance
(TA = +25°C, Frequency = 1.0MHz, V_DD = 1.8V, V_DDQ = 1.5V)
Parameter
Input capacitance (SA, /R, /W, /BW)
Clock input capacitance (K, /K)
Output capacitance (DQ, CQ, /CQ)
Symbol
CIN
CCLK
CI/O
Min
-
-
-
Typ
4
4
5
Max
5
5
6
Unit
pF
pF
pF
Test condition
VIN = 0 V
VCLK = 0 V
VI/O = 0 V
Note
1,2
1,2
1,2
Notes:
1. These parameters are sampled and not 100% tested.
2. Except JTAG (TCK, TMS, TDI, TDO) pins.
AC Test Conditions
Input waveform (Rise/fall time ≤ 0.3 ns)
1.25V
0.25V
0.75V
Test points
0.75V
Output waveform
V_DDQ/2
Test points
V _DDQ/2
R10DS0239EJ0002 Rev.0.02
Dec. 01, 2014
Page 17 of 30