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HD74HC125_15 Datasheet, PDF (8/11 Pages) Renesas Technology Corp – Quad. Bus Buffer Gates (with 3-state outputs) | |||
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HD74HC125, HD74HC126
Waveforms
⢠HD74HC126
⢠Waveform â 1
tr
tf
90 %
90 %
VCC
Input A
50 %
50 %
10 %
10 %
0V
tPLH
tPHL
Output Y
50 %
VOH
50 %
VOL
⢠Waveform â 2
tr
tf
90 %
90 %
VCC
Input C
50 %
50 %
10 %
10 %
0V
tZL
tLZ
Waveform - A
50 %
tZH
10 %
tHZ
VOH
VOL
Waveform - B
50 %
90 %
VOH
VOL
Notes : 1. tr ⤠6 ns, tf ⤠6 ns
2. Input waveform : PRR ⤠1 MHz, duty cycle 50%
3. Waveformâ A is for an output with internal conditions such that the
output is low except when disabled by the output control.
4. Waveformâ B is for an output with internal conditions such that the
output is high except when disabled by the output control.
REJ03D0565-0300 Rev.3.00 Mar 25, 2009
Page 6 of 8
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