HD151TS305RP Datasheet, PDF (8/10 Pages) Renesas Technology Corp – Spread Spectrum Clock for EMI Solution

HD151TS305RP
4. Recommendation of Power–ON Sequence
We recommend usage as power–on sequence Vdd starting profile.
At the time of power–on starting, there is possibility for SSCCKOUT to fix Hi/Low level. Please refer Fig6–1 and
Fig6–2.
VDD
Power
ON
Upper 2.8V
XIN
delay
XIN XOUT
Ref. Clock
Input Timing of XIN
(XIN should be applied after Vdd ≥ 2.8V)
Fig 6–1 In case of reference clock input
VDD
Power
ON
2.8V
XIN
Over 3.5V/msec
Minimal Rising Time
(Vdd rising time should be applied over 3.5V/msec)
Fig 6–2 In case of X’tal reference input
XIN XOUT
X' tal
5. Cycle to Cycle Jitter
We have guaranteed that cycle to cycle jitter will be less than |300ps| at XIN=18MHz, Vdd=3.3V. In case of using XIN
will be less than 15MHz, the cycle to cycle jitter may be over |300ps|. Please notice to consider this point.
Rev.9.00 Jul. 07, 2004 page 8 of 9