HD151TS305RP Datasheet, PDF (4/10 Pages) Renesas Technology Corp – Spread Spectrum Clock for EMI Solution

HD151TS305RP
DC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 0 to 70°C, VDD = 3.3 V±5%
Item
Symbol Min
Typ
Max Unit
Test Conditions
Output voltage
V_OH
3.1
—
—
V
V_OL
—
—
50
mV
Output current *¹
I_OH
—
–40
—
mA
I_OL
—
40
—
Note: 1. Parameters are target of design. Not 100% tested in production.
I_OH = –1 mA, VDD = 3.3 V
I_OL = 1 mA, VDD = 3.3 V
V_OH = 1.5 V
V_OL = 1.5 V
AC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 25°C, VDD = 3.3 V, C_L = 15 pF
Item
Symbol Min
Cycle to cycle jitter ^{*1, 2} t_CCS
—
Typ
| 250 |
Max
| 300 |
Unit
ps
Test Conditions
SSCCLKOUT = 72MHz,
XIN = 18 MHz
Notes
SSC = 0%
SEL1:0 = 10
Fig1
—
| 250 | | 300 |
SSCCLKOUT = 72MHz, SSC = ±0.25%
XIN = 18 MHz
SEL1:0 = 11
Fig1
Output frequency ^{*1, 2}
—
| 250 | | 300 |
CLKOUT=18MHz
Fig1
70.4
—
73.6
MHz SSCCLKOUT = 72MHz, SSC = 0%
XIN = 18 MHz
SEL1:0 = 10
Slew rate^*1
t_SL
Clock duty cycle ^*1
Output impedance ^*1
70.3
—
0.8
—
45
50
—
40
73.7
SSCCLKOUT = 72MHz, SSC= ±0.25%
XIN = 18 MHz
SEL1:0 = 11
—
V/ns XIN = 18 MHz CLKOUT 0.4 V to 2.4 V
55
%
—
Ω
Spread spectrum
modulation frequency ^*1
—
33
—
KHz SSCCLKOUT = 96MHz,
XIN = 24 MHz
Input clock frequency
Stabilization time ^*1,3
15
—
40
MHz
—
—
2
ms
Note: 1. Parameters are target of design. Not 100% tested in production.
2. Cycle to cycle jitter and output frequency are included spread spectrum modulation.
3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after
power up.
SSCCLKOUT
(or CLKOUT)
tcycle n
tcycle n+1
t _CCS = (tcycle n) - (tcycle n+1)
Figure 1 Cycle to cycle jitter
Rev.9.00 Jul. 07, 2004 page 4 of 9