H8S2258 Datasheet, PDF (773/1071 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 16 I²C Bus Interface (IIC) (Option)
SDA
SCL
A
Transmit data
A
Confirm
9 1 2 3 4 5 6 7 8 SCL = L
Transmit data
9 123
BC2 to BC0
0
IRIC
(sampling
example)
7 6 5 4 3 21
IRIC flag can be cleared
0
765
IRIC clear
IRIC clear when
BC2 to BC0 ≥ 2
IRIC flag can be cleared
IRIC flag can not be cleared
Figure 16.28 IRIC Flag Clearing Timing in Wait Operation
17. Interrupt during Module Stop Mode
When the module is stopped in the state that an interrupt is requested, the interrupt source of
the CPU or activation source of the DTC is not cleared. Be sure to enter module stop mode by
disabling the interrupt beforehand.
16.6.1 Module Stop Mode Setting
IIC operation can be disabled or enabled using the module stop control register. The initial setting
is for IIC operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 24, Power-Down Modes.
Rev. 5.00 Aug 08, 2006 page 687 of 982
REJ09B0054-0500