H8S2258 Datasheet, PDF (254/1071 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 7 Bus Controller
7.3.1 Bus Width Control Register (ABWCR)
ABWCR designates each area for either 8-bit access or 16-bit access.
ABWCR sets the data bus width for the external memory space. The bus width for on-chip
memory and internal I/O registers is fixed regardless of the settings in ABWCR.
Bit Bit Name Initial Value R/W
7 ABW7
1/0*
R/W
6 ABW6
1/0*
R/W
5 ABW5
1/0*
R/W
4 ABW4
1/0*
R/W
3 ABW3
1/0*
R/W
2 ABW2
1/0*
R/W
1 ABW1
1/0*
R/W
0 ABW0
1/0*
R/W
Description
Area 7 to 0 Bus Width Control
These bits select whether the corresponding area is to
be designated for 8-bit access or 16-bit access.
0: Area n is designated for 16-bit access
1: Area n is designated for 8-bit access
Note: n = 7 to 0
Note: * In modes 5 to 7, initial value of each bit is 1. In mode 4, initial value of each bit is 0.
7.3.2 Access State Control Register (ASTCR)
ASTCR designates each area as either a 2-state access space or a 3-state access space.
ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
Bit Bit Name Initial Value R/W
7 AST7
1
R/W
6 AST6
1
R/W
5 AST5
1
R/W
4 AST4
1
R/W
3 AST3
1
R/W
2 AST2
1
R/W
1 AST1
1
R/W
0 AST0
1
R/W
Description
Area 7 to 0 Access State Control
These bits select whether the corresponding area is to
be designated as a 2-state access space or a 3-state
access space. Wait state insertion is enabled or disabled
at the same time.
0: Area n is designated for 2-state access
Wait state insertion in area n external space is
disabled
1: Area n is designated for 3-state access
Wait state insertion in area n external space is
enabled
Note: n = 7 to 0
Rev. 5.00 Aug 08, 2006 page 168 of 982
REJ09B0054-0500