32180 Datasheet, PDF (728/839 Pages) Renesas Technology Corp – 32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series

19
JTAG
19.4 Basic Operation of JTAG
19.4.3 DR Path Sequence
The data register that was selected in the IR path sequence prior to the DR path sequence is operated on to
inspect or set data in it. The DR path sequence is performed following the procedure described below.
(1) From the Run-Test/Idle state, apply JTMS = high for a period of 1 JTCK cycle to enter the Select-DR-
Scan state. Which data register will be selected at this time depends on the instruction that was set during the
IR path sequence performed prior to the DR path sequence.
(2) Apply JTMS = low to enter the Capture-DR state. At this time, the result of boundary-scan test or the fixed
data defined for each register is set in the data register’s shift register stage.
(3) Proceed and apply JTMS = low to enter the Shift-DR state. In the Shift-DR state, the DR value is shifted
right one bit every cycle, and the data that was set in (2) is serially output from the JTDO pin. At the same
time, setup data is set in the data register’s shift register stage bit by bit as it is serially fed from the JTDI pin.
By continuing the Shift-IR state as long as the number of bits that comprise the selected data register (by
applying JTMS = low), all bits of data can be set in and read out from the shift register stage. To stop the shift
operation in the middle, enter the Pause-DR state temporarily via the Exit1-DR state (by setting JTMS input
from high to low). To return from the Pause-DR state, enter the Shift-DR state temporarily via the Exit2-DR
state (by setting JTMS input from high to low).
(4) Apply JTMS = high to move from the Shift-DR state to the Exit1-DR state. This completes the shift operation.
(5) Proceed and apply JTMS = high to enter the Update-DR state. In the Update-DR state, the data that was
set in the data register’s shift register stage is transferred to the parallel output stage, and the setup data is
thereby made ready for use.
(6) Proceed and apply JTMS = high to enter the Select-DR-Scan state or JTMS = low to enter the Run-Test/Idle state.
JTCK
JTMS
JTDI input is sampled at rise of
JTCK in the Shift-DR state.
Setup data is set in the parallel output stage
at fall of JTCK in the Update-DR state.
TAP
states
JTDI
Don't Care
JTDO
LSB value
High impedance
Don't Care
MSB value
High impedance
JTDO is output at fall of
JTCK in the Shift-DR state.
Finished storing setup data in
the selected data register's
shift register stage.
Note: • Because all bits in the data register's shift register stage also are shifted right, data is output from JTDO
beginning with the LSB. Similarly, data is supplied to JTDI beginning with the LSB.
Figure 19.4.4 DR Path Sequence
19-9
32180 Group User's Manual (Rev.1.0)