H8S-2437 Datasheet, PDF (723/746 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

24.3.4 Timing of On-Chip Peripheral Modules
Tables 24.8 to 24.10 show the on-chip peripheral module timing.
Table 24.8 Timing of On-Chip Peripheral Modules
Condition: V_CC = 3.0 V to 3.6 V, V_SS = 0 V, φ = 5 MHz to 20 MHz
Item
Symbol Min.
I/O ports Output data delay time
t_PWD

Input data setup time
t_PRS
20
Input data hold time
t_PRH
20
FRT
Timer output delay time
t_FTOD

Timer input setup time
t_FTIS
20
Timer clock input setup time
t_FTCS
20
Timer clock pulse Single edge t_FTCWH
1.5
width
Both edges
t_FTCWL
2.5
TPU
Timer output delay time
t_TOCD

Timer input setup time
t_TICS
25
Timer clock input setup time
t_TCKS
25
Timer clock pulse Single edge t_TCKWH
1.5
width
Both edges
t_TCKWL
2.5
TMR Timer output delay time
t_TMOD

Timer reset input setup time
t_TMRS
25
Timer clock input setup time
t_TMCS
25
Timer clock pulse
Single edge t_TMCWH
1.5
width
Both edges
t_TMCWL
2.5
PWM, Pulse output delay time
PWMX
t_PWOD

SCI
Input clock cycle
Asynchronous t_Scyc
4
Synchronous
6
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
(synchronous)
t_SCKW
t_SCKr
t_SCKf
t_TXD
0.4



Receive data setup time
(synchronous)
t_RXS
40
Receive data hold time (synchronous) t_RXH
40
A/D
Trigger input setup time
converter
t_TRGS
30
Max.
40


40




40




40




40


0.6
1.5
1.5
40



Unit
ns
t_cyc
ns
t_cyc
ns
t_cyc
ns
t_cyc
t_Scyc
t_cyc
ns
Test Conditions
Figure 24.14
Figure 24.15
Figure 24.16
Figure 24.17
Figure 24.18
Figure 24.19
Figure 24.21
Figure 24.20
Figure 24.22
Figure 24.23
Figure 24.24
Figure 24.25
Rev. 1.00, 09/03, page 685 of 704