H8S-2437 Datasheet, PDF (375/746 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

12.5.4 Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock at overflow/underflow of TCNT_2 as
set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase counting mode.
Table 12.18 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the
counter operates independently in phase counting mode.
Table 12.18 Cascaded Combinations
Combination
Channels 1 and 2
Upper 16 Bits
TCNT_1
Lower 16 Bits
TCNT_2
Example of Cascaded Operation Setting Procedure:
Figure 12.21 shows an example of the setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1] Set bits TPSC2 to TPSC0 in the channel 1 TCR
to B'111 to select TCNT_2 overflow/underflow
counting.
[2] Set the CST bit in TSTR for the upper and lower
[1]
channel to 1 to start the count operation.
Start counting
[2]
<Cascaded operation>
Figure 12.21 Cascaded Operation Setting Procedure
Examples of Cascaded Operation:
Figure 12.22 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the
TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
Rev. 1.00, 09/03, page 337 of 704