R5F56108VNFP_13 Datasheet, PDF (71/86 Pages) Renesas Technology Corp – RENESAS 32-Bit MCU

RX610 Group
5. Electrical Characteristics
Table 5.8 Timing of On-Chip Peripheral Modules (2)
Conditions: VCC = PLLVCC = AVCC = 3.0 to 3.6 V, VREFH = 3.0 V to AVCC, VSS = PLLVSS = VREFL = 0 V, PCLK = 8 to 50 MHz
Ta = -20 to +85°C (regular specifications), Ta = -40 to +85°C (wide-range specifications)
Item
Symbol Min. *¹*²
Max.
Test
Unit Conditions
RIIC
SCL input cycle time
tSCL
8(10) x (1/PCLK) + 1300 
ns Figure 5.25
(Standard-mode) _{SCL input high pulse width}
tSCLH
3(5) x (1/PCLK) + 300 
ns
ICFER.FMPE = 0 _{SCL input low pulse width}
tSCLL
5x (1/PCLK) + 1000

ns
SCL, SDA input rising time
tSr

1000
ns
SCL, SDA input falling time
tSf

300
ns
SCL, SDA input spike pulse removal tSP
0
time
4 x (1/PCLK) ns
SDA input bus free time
tBUF
5x (1/PCLK) + 1000

ns
Start condition input hold time
tSTAH
Re-start condition input setup time tSTAS
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
RIIC
SCL input cycle time
(Fast-mode)
SCL input high pulse width
ICFER.FMPE = 0 _{SCL input low pulse width}
tSTOS
tSDAS
tSDAH
Cb
tSCL
tSCLH
tSCLL
SCL, SDA input rising time
tSr
SCL, SDA input falling time
tSf
SCL, SDA input spike pulse removal tSP
time
SDA input bus free time
tBUF
Start condition input hold time
tSTAH
Re-start condition input setup time tSTAS
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacitive load
tSTOS
tSDAS
tSDAH
Cb
3(5) x (1/PCLK) + 300 
ns
5x (1/PCLK) + 1000

ns
3(5) x (1/PCLK) + 300 
ns
250

ns
0

ns

400
pF
8(10) x (1/PCLK) + 600 
ns
3(5) x (1/PCLK) + 300 
ns
5 x (1/PCLK) + 300

ns
20 + 0.1Cb
300
ns
20 + 0.1Cb
300
ns
0
4 x (1/PCLK) ns
5 x (1/PCLK) + 300

ns
3(5) x (1/PCLK) + 300 
ns
5 x (1/PCLK) + 300

ns
3(5) x (1/PCLK) + 300 
ns
100

ns
0

ns

400
pF
R01DS0097EJ0120 Rev.1.20
Feb 20, 2013
Page 71 of 84