R5F56108VNFP_13 Datasheet, PDF (48/86 Pages) Renesas Technology Corp – RENESAS 32-Bit MCU

RX610 Group
Address
0008 81C2h
0008 81C4h
0008 81C5h
0008 81C6h
0008 81C8h
0008 81CAh
0008 81D0h
0008 81D1h
0008 81D2h
0008 81D4h
0008 81D5h
0008 81D6h
0008 81D8h
0008 81DAh
0008 81E6h
0008 81E7h
0008 81E8h
0008 81E9h
0008 81EAh
0008 81EBh
0008 81ECh*¹
0008 81EDh*²
0008 81EEh*¹
0008 81EFh*²
0008 81F0h
0008 81F6h
0008 81F7h
0008 81F8h
0008 81F9h
0008 81FAh
0008 81FBh
0008 81FCh*³
0008 81FDh*⁴
0008 81FEh*³
0008 81FFh*⁴
0008 8200h
0008 8201h
0008 8202h
0008 8203h
0008 8204h
0008 8205h
0008 8206h
0008 8207h
0008 8208h
0008 8209h
Module
Abbreviation Register Name
TPU10
Timer I/O control register
TPU10
Timer interrupt enable register
TPU10
Timer status register
TPU10
Timer counter
TPU10
Timer general register A
TPU10
Timer general register B
TPU11
Timer control register
TPU11
Timer mode register
TPU11
Timer I/O control register
TPU11
Timer interrupt enable register
TPU11
Timer status register
TPU11
Timer counter
TPU11
Timer general register A
TPU11
Timer general register B
PPG0
PPG output control register
PPG0
PPG output mode register
PPG0
Next data enable register H
PPG0
Next data enable register L
PPG0
Output data register H
PPG0
Output data register L
PPG0
Next data register H
PPG0
Next data register L
PPG0
Next data register H
PPG0
Next data register L
PPG1
PPG trigger select register
PPG1
PPG output control register
PPG1
PPG output mode register
PPG1
Next data enable register H
PPG1
Next data enable register L
PPG1
Output data register H
PPG1
Output data register L
PPG1
Next data register H
PPG1
Next data register L
PPG1
Next data register H
PPG1
Next data register L
TMR0
Timer control register
TMR1
Timer control register
TMR0
Timer control/status register
TMR1
Timer control/status register
TMR0
Time constant register A
TMR1
Time constant register A
TMR0
Time constant register B
TMR1
Time constant register B
TMR0
Timer counter
TMR1
Timer counter
R01DS0097EJ0120 Rev.1.20
Feb 20, 2013
4. I/O Registers
Register
Number
Abbreviation of Bits
TIOR
8
TIER
8
TSR
8
TCNT
16
TGRA
16
TGRB
16
TCR
8
TMDR
8
TIOR
8
TIER
8
TSR
8
TCNT
16
TGRA
16
TGRB
16
PCR
8
PMR
8
NDERH
8
NDERL
8
PODRH
8
PODRL
8
NDRH
8
NDRL
8
NDRH
8
NDRL
8
PTRSLR
8
PCR
8
PMR
8
NDERH
8
NDERL
8
PODRH
8
PODRL
8
NDRH
8
NDRL
8
NDRH
8
NDRL
8
TCR
8
TCR
8
TCSR
8
TCSR
8
TCORA
8
TCORA
8
TCORB
8
TCORB
8
TCNT
8
TCNT
8
Number of
Access Access
Size
Cycles
8
8
8
16
16
16
8
8
8
8
8
16
16
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8 or 16
8 or 16*⁵
8 or 16
8 or 16*⁵
8 or 16
8 or 16*⁵
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
2 to 3 PCLK ^*7
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