M30218_01 Datasheet, PDF (71/469 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER

FLD controller
Mitsubishi microcomputers
M30218 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FLDC mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FLDM
Address
035016
When reset
0016
Bit symbol
Bit name
Function
RW
FLDM0
Automatic display
control bit
0 : General-purpose mode
1 : Automatic display mode
FLDM1 ^{Display start bit}
0 : Stop display
1 : Display
(start to display by switching “0” to “1”)
FLDM2
FLDM3
FLDM4
Tscan control bits
Timing number control bit
b3b2
00 : FLD digit interrupt
(at rising edge of each digit)
} ^{01 : 1 X Tdisp}
10 : 2 X Tdisp
FLD blanking
interrupt (at falling
edge of last digit)
11 : 3 X Tdisp
0 : 16 timing mode
1 : 32 timing mode
FLDM5
Gradation display mode
selection control bit
0 : Not selecting
1 : Selecting (Note )
FLDM6
Tdisp counter
0 : f(XIN)/32
count source selection bit _{1 : f(XIN)/128}
FLDM7
High-breakdown voltage
port drivability select bit
0 : Drivability strong
1 : Drivability weak
Note : When a gradation display mode is selected, a number of timing is max. 16 timing.
(Set the timing number control bit to “0”.)
FLD output control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FLDCON
Address
035116
When reset
0016
Bit symbol
Bit name
Function
FLDCON0 ^{P44 to P47 FLD}
output reverse bit
0 : Output normally
1 : Reverse output
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
FLDCON2 ^{P44 to P47 FLD}
Toff is invalid bit
0 : Perform normally
1 : Toff is invalid
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
FLDCON4 ^{P97 dimmer output}
control bit
0 : Output normally
1 : Dimmer output
FLDCON5 ^{CMOS ports: section of}
Toff generate/not
0 : section of Toff does NOT generate
1 : section of Toff generates
generate bit
FLDCON6 ^{High-breakdown-voltage ports: 0 : section of Toff does NOT generate}
section of Toff
1 : section of Toff generates
generate/not generate bit
RW
FLDCON7 ^Toff2
SET/RESET change bit
0 : gradation display data is reset at Toff2
(set at Toff1)
1 : gradation display data is set at Toff2
(reset at Toff1)
Tdisp time set register
b7
b0
Symbol
TDISP
Address
035216
When reset
0016
Function
Counts Tdisp time. Count source is selected by Tdisp
counter count source select bit.
Values that can be set R W
016 to FF16
Figure 39. FLDC-related Register(1)
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