R1Q2A3636 Datasheet, PDF (7/25 Pages) Renesas Technology Corp – 36-Mbit QDR™II SRAM 2-word Burst

R1Q2A3636/R1Q2A3618/R1Q2A3609
2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable
Status
Power Up
Unstable
Clock Stage
Stop
Clock Stage
NOP & DLL
Locking Stage
V_DD
V_DDQ
V_REF
/DOFF
30ns min.
1024cycle min.
C, /C, K, /K
Normal
Operation
DLL Constraints
1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as
TKC var.
2. The lower end of the frequency at which the DLL can operate is 100MHz.
Programmable Output Impedance
1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ).
The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance
matching with a tolerance of 10% is 250 Ω typical.
The total external capacitance of ZQ ball must be less than 7.5 pF.
REJ03C0294-0003 Rev.0.03 Jul. 31, 2007
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