R1Q2A3636 Datasheet, PDF (10/25 Pages) Renesas Technology Corp – 36-Mbit QDR™II SRAM 2-word Burst

R1Q2A3636/R1Q2A3618/R1Q2A3609
Bus Cycle State Diagram
/R = H
/R = H
Read Port NOP
R_Init = 0
/R = L
Supply voltage
provided
Power Up
Load New
Read Address
Always
/R = L
Read Double
Supply voltage
provided
Write Port NOP
/W = L
Load New
Write Address
at /K↑
Always
/W = L
Write Double
at /K↑
/W = H
/W = H
Notes: 1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order
is always fixed as: xxx…xxx+0, xxx…xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
2. Read and write state machines can be active simultaneously.
3. State machine control timing sequence is controlled by K.
REJ03C0294-0003 Rev.0.03 Jul. 31, 2007
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