M66255FP Datasheet, PDF (7/14 Pages) Mitsubishi Electric Semiconductor – 8192 x 10-BIT LINE MEMORY (FIFO)

M66255FP
Matters that Needs Attention when WCK Stops
WCK
n cycle n + 1 cycle
t_WCK
WE
t_DS t_DH
Dn
(n)
n cycle
Disable cycle
t_NWES
t_DS t_DH
(n)
Period for writing data (n)
into memory
Period for writing data (n)
into memory
WRES = "H"
Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level
period of n + 1 cycle. The writing operation is complete at the falling edge after n + 1 cycle.
To stop reading write data at n cycle, enter WCK before the rising edge after n + 1 cycle.
When the cycle next to n cycle is a disable cycle, WCK for a cycle requires to be entered after the disable cycle as well.
REJ03F0249-0200 Rev.2.00 Sep 14, 2007
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