HM64YLB36512 Datasheet, PDF (7/31 Pages) Renesas Technology Corp – 16M Synchronous Late Write Fast Static RAM (512-kword × 36-bit)

HM64YLB36512 Series
Programmable Impedance Output Drivers
Output buffer impedance can be programmed by terminating the ZQ pin to V_SS through a precision resistor (RQ). The
value of RQ is five times the output impedance desired. The allowable value of RQ to guarantee impedance matching
with a tolerance of 15% is 250 Ω. If the status of ZQ pin is open, output impedance is maximum value. Maximum
impedance also occurs with ZQ connected to V_DDQ. The impedance update of the output driver occurs when the SRAM
is in high-Z. Write and deselect operations will synchronously switch the SRAM into and out of high-Z, therefore will
trigger an update. At power up, the output buffer is in high-Z. It will take 4,096 cycles for the impedance to be
completely updated.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit Notes
Input voltage on any pin
VIN
−0.5 to VDDQ + 0.5
V
1, 4
Core supply voltage
VDD
−0.5 to +3.13
V
1
Output supply voltage
VDDQ
−0.5 to +2.1
V
1, 4
Operating temperature
TOPR
0 to +85
°C
Storage temperature
TSTG
−55 to +125
°C
Output short-circuit current
IOUT
25
mA
Latch up current
ILI
200
mA
Package junction to top thermal resistance
θJ-top
6.5
°C/W 5
Package junction to board thermal resistance
θJ-board 12
°C/W 5
Notes: 1. All voltage is referenced to VSS.
2. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted the operation conditions. Exposure to higher voltages than recommended voltages for
extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the
tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
Remember, according to the absolute maximum ratings table, VDDQ is not to exceed 2.1 V, whatever the
instantaneous value of VDDQ.
5. See figure below.
θJ-top
θJ-board
Thermocouple
Thermo grease
Teflon block
Thermocouple
Water
Cold plate
SRAM
Teflon block
Water
SRAM
JEDEC/2S2P BGA
Thermal board
Water
Thermo grease
Cold plate
Water
JEDEC/2S2P BGA
Thermal board
Rev.3.00 Jan 13, 2006 page 7 of 29