HM64YLB36512 Datasheet, PDF (1/31 Pages) Renesas Technology Corp – 16M Synchronous Late Write Fast Static RAM (512-kword × 36-bit)

HM64YLB36512 Series
16M Synchronous Late Write Fast Static RAM
(512-kword × 36-bit)
REJ03C0270-0300
Rev.3.00
Jan.13.2006
Description
The HM64YLB36512 is a synchronous fast static RAM organized as 512-kword × 36-bit. It has realized high speed
access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most
appropriate for the application which requires high speed, high density memory and wide bit width configuration, such
as cache and buffer memory in system. It is packaged in standard 119-bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
• 2.5 V ± 5% operation and 1.5 V (V_DDQ)
• 16M bit density
• Byte write control (4 byte write selects, one for each 9-bit)
• Optional ×18 configuration
• HSTL compatible I/O
• Programmable impedance output drivers
• Asynchronous G output control
• Asynchronous sleep mode
• FC-BGA 119pin package with SRAM JEDEC standard pinout
• Limited set of boundary scan JTAG IEEE 1149.1 compatible
• Mode selectable among late write, associative late write (late select) and register-latch
• Late select mode:
 Synchronous register to register operation
 Late SAS select, selects which half of 72-bit core data to return on reads
 SAS serves as way select
 Differential HSTL clock inputs
• Late write mode:
 Synchronous register to register operation
 Differential HSTL clock inputs
• Register-latch mode:
 Synchronous register to latch operation
 Differential pseudo-HSTL clock inputs
Rev.3.00 Jan 13, 2006 page 1 of 29