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HD74LV166A_10 Datasheet, PDF (7/10 Pages) Renesas Technology Corp – Parallel-Load 8-bit Shift Register | |||
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HD74LV166A
Preliminary
Switching Characteristics (cont)
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Hold time
Pulse width
Symbol
fmax
tPLH/tPHL
tPHL
tsu
th
tw
Ta = 25°C
Min Typ Max
110 165 â
95 125 â
â 6.0 9.9
â 7.7 11.9
â 5.4 8.6
â 6.9 10.6
3.5 â â
3.5 â â
4.5 â â
4.0 â â
4.0 â â
1.0 â â
1.0 â â
1.0 â â
5.0 â â
4.0 â â
Ta = â40 to 85°C
Min Max
90
â
85
â
1.0
11.5
1.0
13.5
1.0
10.0
1.0
12.0
3.5
â
3.5
â
4.5
â
4.0
â
4.0
â
1.0
â
1.0
â
1.0
â
5.0
â
4.0
â
Unit
MHz
ns
ns
ns
ns
Test
Conditions
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
(VCC = 5.0 ± 0.5 V)
FROM
TO
(Input) (Output)
CLK
QH
CLR
CLR inactive before
CLK ï
CLK INH before CLK ï
Data before CLK ï
SH/LD high before CLK
ï
SER before CLK ï
PAR data after SH/LD ï
SER data after CLK ï
SH/LD high after CLK ï
CLR low
CLK H or L
Operating Characteristics
Item
Power dissipation capacitance
Symbol
CPD
VCC (V)
3.3
5.0
Ta = 25°C
Min
Typ
Max
â
36.1
â
â
37.5
â
(CL = 50 pF)
Unit Test Conditions
pF f = 10 MHz
Test Circuit
Measurement point
CL*
Note: CL includes the probe and jig capacitance.
R04DS0002EJ0400 Rev.4.00
Aug 16, 2010
Page 7 of 9
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